A clock generation circuit for generating a clock signal to be used for data reception is used in a reception circuit used for communication inside a large scale integrated circuit (LSI) chip (hereinafter abbreviated as a “chip”) or communication between chips. As the clock generation circuit, there is a clock data recovery (CDR) circuit for recovering a value (data) and a clock signal from a data signal. In the CDR circuit, in order to perform data determination (sampling) at an appropriate timing, a phase difference between the clock signal for data determination and the data signal is detected, and the phase of the clock signal is adjusted.
In recent years, with improvement in the performance of information processing apparatuses such as communication trunk apparatuses and servers, the information processing speed in an apparatus and in a chip has also been increased and the data rate of a data signal transmitted in the apparatus has become high. With the increase in the data rate, the fluctuation (jitter) of the data signal or the clock signal in the time axis direction has a greater influence on a bit error rate (BER) which is an index as to whether or not the value of the data signal may be correctly determined.
In order to detect a BER, there has been conventionally proposed a CDR circuit including an eye monitor function. The eye monitor function is implemented by, for example, a circuit (eye sampler) that determines the value of a data signal using a clock signal that may be adjusted in phase, which is different from the clock signal used in the phase control circuit described above, or a circuit that calculates the BER based on an output value of the eye sampler.
Related techniques are disclosed in, for example, Japanese Laid-Open Patent Publication No. 2014-174131.